High-throughput local oxidation nanolithographic process

ABSTRACT

In a lithographic process suitable for use in the manufacture of electronic components, oxidative reactions are employed to reproducibly fabricate patterns having micro- or nano-scale dimensions. An electrically-conductive template is fabricated to have a nanometer-scale sharp edge and describe a pattern having a micron-scale length. The oxidative reaction is mediated by a water meniscus connecting the sharp edge of the template and an oxidizable substrate. One suitable substrate is graphene. The template can be controllably positioned using a light lever method.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims benefit of U.S. Provisional Patent Application Ser. No. 61/164,101, filed Mar. 27, 2009, and U.S. Provisional Patent Application Ser. No. 61/216,298, filed May 16, 2009, both of which are incorporated by reference herein.

STATEMENT REGARDING FEDERALLY-FUNDED RESEARCH

Not applicable.

FIELD OF THE INVENTION

The present invention relates to lithographic processes suitable for use in the manufacture of electronic components, more particularly, a lithography process employing oxidative reactions to fabricate patterns having micro- or nano-scale dimensions.

BACKGROUND OF THE INVENTION

Features having micro and nano-scale dimensions can be etched into oxidizable materials by a lithographic technique known as local anodic oxidation. In air or other humid atmospheres, structures, such as the tip of an atomic force microscope (AFM), are covered by thin films of ambient water. As illustrated in FIG. 1, when an AFM tip 10 sufficiently close to, but not touching, the surface 12 of a substrate 14, a capillary effect causes the adsorbed layer of water to form a water meniscus 16, electrically linking the tip 10 to the substrate 14. The water meniscus 16 is dragged along the substrate 12 by moving the tip 10 in a spatial scan. A voltage is applied across the tip 10 and the substrate 14 to dissociate water in the meniscus to hydrogen ion (H⁺) and hydroxyl ion (OH⁻), thus oxidizing the substrate 14. The voltage is maintained for a hold time sufficient to remove the substrate to the desired depth or width. Removal of the oxidized material (not shown) leaves a trench 18 in the substrate 14, the shape of which follows the pattern traced by the tip. For graphene-based materials, the oxidized carbon is typically volatilized as carbon dioxide.

Process parameters such as applied voltage, hold time, radius of curvature of the tip, the distance between the tip, and ambient humidity, can be varied during the etching process to control the dimensions of the features. Increasing the applied voltage across the tip 10 and substrate 14 increases the rate at which H+ and OH− are generated, thus increasing the rate at which the substrate 14 is oxidized and creating a wider (or deeper) trench 18. Increasing the hold time also increases the width or depth of the trench 18, because of the increased duration of the oxidative reactions. Increasing the radius of curvature of the tip, decreasing the distance between the tip and the substrate, or increasing the humidity in the environment of the tip each results in a wider meniscus, and thus a wider etched feature.

SUMMARY OF THE INVENTION

In a method of reproducibly forming a pattern having a nanoscale dimension in an oxidizable substrate, a templated chip is fabricated so as to have an electrically-conductive raised template with an edge having a width that is less than about 30 nm and describing a pattern having a length of at least 1000 nm along one dimension of the pattern. The template is positioned over the oxidizable substrate in an atmosphere having a relative humidity of at least 20%, such that a water meniscus forms an electrical connection between the edge of the template and the substrate. In some embodiments of the invention, the distance between the edge of the template and the substrate is in the range of about 20 nm to about 50 nm. A voltage is then applied across the template and the substrate so as to oxidize substrate material that is in contact with the meniscus. The templated chip can be positioned using an electrically-conductive positioning sensor by application of the light lever principle.

BRIEF DESCRIPTION OF THE FIGURES

For a better understanding of the present invention, reference is made to the following detailed description of the exemplary embodiments considered in conjunction with the accompanying drawings, in which:

FIG. 1 is a sequenced set of schematic drawings illustrating a single-tip etching process for formation of micro- or nano-scale patterns according to the prior art;

FIG. 2 is a schematic representation of a dielectric substrate being etched by a serial single-tip local oxidation process;

FIG. 3 is a schematic representation of a dielectric substrate that has been etched by a serial single-tip local oxidation process to form quantum dots of a dielectric material;

FIG. 4 is a schematic hierarchical diagram showing two levels of detail of a single-electron transistor comprising quantum dots;

FIG. 5 is a schematic view of a templated chip for forming a micro- or nano-scale pattern on a surface during a nanolithographic process according to an embodiment of the present invention;

FIG. 6 is a schematic view of an assembly comprising the templated chip of FIG. 5 on a position sensor for use with an atomic force microscope according to an embodiment of the present invention;

FIG. 7 is schematic front view of the assembly of FIG. 6 positioned over a substrate during a nanolithographic process according to an embodiment of the present invention;

FIG. 8 is a schematic top orthogonal view of the substrate of FIG. 7 after the nanolithographic process of FIG. 7;

FIG. 9 is a schematic view of a templated chip according to an embodiment of the present invention, that is configured to produce a single-electron transistor having the same pattern as that of FIG. 4;

FIG. 10 is a schematic corner view of the template of FIG. 9 positioned over a substrate during a nanolithographic process according to an embodiment of the present invention;

FIG. 11 is a schematic top orthogonal view of the substrate of FIG. 10 after the anodic oxidative flash-patterning process of FIG. 10;

FIGS. 12A-12G are a sequenced set of schematic diagrams illustrating steps in a method of producing a templated chip for use in a nanolithographic process according to an embodiment of the present invention;

FIG. 13 is a schematic bottom orthogonal view of a templated chip on a positioning sensor for use in a nanolithographic process according to an embodiment of the present invention;

FIG. 14 is a front schematic view of the templated chip and positioning sensor of FIG. 13 during a nanolithographic process according to an embodiment of the present invention;

FIGS. 15A-15I are a sequenced set of schematic diagrams illustrating steps in a method of producing a position sensor according to an embodiment of the present invention;

FIG. 16 is a schematic end view of a templated chip set in the position sensor of FIG. 15I;

FIG. 17 is a bottom orthogonal view of the templated chip and position sensor of FIG. 16;

FIG. 18 is a data plot showing a relationship between the size of features formed in a substrate by a single-tip oxidative etching process at high humidity and the distance between the AFM tip used in the etching process and the substrate;

FIG. 19 is a data plot showing a relationship between the size of features formed in a substrate by single-tip oxidative etching process at low humidity and the distance between the AFM tip used in the etching process and the substrate and

FIG. 20 is a plot showing a relationship between feature width and hold times in a single-tip oxidative etching process.

DETAILED DESCRIPTION OF THE INVENTION

Conventional AFM oxidation lithographic processes are inherently serial since they rely on a single AFM tip to fabricate the entire pattern. For example, to fabricate a single 3 μm long trench in graphene, the tip may be moved pixel by pixel at a scan speed of 0.05 μm/s. While such a trench may be fabricated in minutes, repeating a pattern of 20 or 30 longer trenches over a 100 μm² area would take hours. For example, FIG. 2 is a schematic illustration of a portion 20 of a graphene layer 22 on a silicon dioxide substrate 24 being etched using a single AFM tip 26, exposing silicon dioxide 24 to define a series of quantum dots 28 surrounded by trenches 30, which serve as electron tunneling barriers. The completed portion 20 is shown as FIG. 3. Such structures could be used in a single or thin-layer graphene transistor 32 made according to an embodiment of the present invention. A schematic representation of such a transistor 32, without electrical leads, is shown in FIG. 4 in relation to the portion 20 of the graphene layer 22 of FIG. 3. Such a transistor 32 could be on the order of a few square microns, but would require hours to fabricate using an AFM tip because of its complexity. Further, AFM tip material tends to be hydrophilic silicon. If the substrate is hydrophobic, like graphene, the moving tip tends to pick up the water meniscus and separate it from the substrate. This effect tends to leave undesirable gaps in the pattern, decreasing the utility of any structure formed by that method. For these reasons, it is impractical to etch complex patterns using AFM tip lithography.

According to an embodiment of the present invention, a flash lithography technique, based on the general principles of AFM-tip local oxidation described above, can be used to precisely and controllably fabricate complex, large-area structures having nanoscale features (i.e., “nanostructures”). Such nanostructures can be produced at much higher rates by the disclosed flash lithography technique than by single-tip techniques. In brief, an electrically-conductive silicon chip is prepared with a raised template that can repeatedly create large-area nanostructures of any two-dimensional morphology on any material which can be locally oxidized. The pattern of the template is transferred to the substrate in a single flash-patterning step. Exemplary embodiments of the invention are discussed herein with respect to graphene substrates, but the technique may be applied to other substrates that are susceptible to local oxidation. For the purposes of the present disclosure a nanoscale feature is one having at least one dimension of less than 1000 nm, preferably in the range of about 10 nm to about 100 nm. In principle, line widths as small as 20 nm can be achieved using the flash lithography method disclosed herein.

In a nanolithographic method according to an embodiment of the present invention, a position sensor is magnetically attached to the magnetic scanner of an AFM, and a templated silicon chip, such as that described above, is placed therein with the templated surface of the chip (i.e., the template) facing outward. Useful embodiments of the position sensor and templated chips are discussed elsewhere herein. By means of the AFM, the template is brought into close proximity to an oxidizable substrate (e.g., a layer of graphene on silicon dioxide). In some embodiments of the method, the template is brought to within 20 nm to 50 nm of the substrate. The ambient relative humidity in the environment of the template is adjusted to a user-defined value in the range of from about 20% to about 60%, causing the formation of a water meniscus between the template and the substrate that bridges the template and substrate and shadows the pattern of the template. A voltage is applied across the templated chip and the substrate for a set patterning time (i.e., a hold time), oxidizing the substrate only where it is linked to the template through the water meniscus. In some embodiments of the invention, the voltage is in the range of from about −4V to about −10V, and the hold time is in the range of from about 60 milliseconds (ms) to about 100 ms, depending on the material to be oxidized and the values of other process parameters. As a result of the oxidation, a pattern is formed in the substrate that matches the pattern of the template. Process parameters such as applied voltage, hold time, radius of curvature of the tip, the distance between the tip, and ambient humidity, can be varied during the nanolithographic process to control the dimensions of the features in the patterned substrate. The aforesaid nanolithographic method and the apparatus used to implement the method are described more fully with respect to the figures and examples discussed hereinbelow.

FIG. 5 is schematic illustration of an exemplary templated silicon chip 34 that is suitable for use in a flash lithography technique according to an embodiment of the present invention. The templated chip 34 includes an electrically-conductive template 36 having a sharp edge 38 in the form of a letter “S”. The template 36 is integral with the silicon body 40 of the chip 34, which also has a metallic layer 42 opposite the template 36. In an embodiment of the present invention, the sharp edge 38 has a width in the range of about 10 nm to about 30 nm, with the width being limited by the method used to make the template 36 and the material of which the template 36 is made. An exemplary method of making such a chip 34 is described elsewhere herein.

FIG. 6 is a schematic illustration of the chip 34 mounted on a position sensor 44 for positioning the chip 34. The position sensor 44 includes a silicon body 46 with a substantially flat face 48 having a recess (not shown) therein for receiving the chip 34. The chip 34 is placed in the recess such that the template 36 faces outward from the position sensor 44. The position sensor 44 further includes a number of cantilevers 50 having sharp tips 52 that extend away from the silicon body 46. In some configurations, such as that of FIG. 6, the arms 50 may be roughly co-planar with the face 48, and the tips 52 may be structurally similar to AFM tips. However, the cantilevers 50 are not necessary co-planar with the face 48, or even straight (see, e.g., FIG. 7). The cantilevers 50 and the tips 52 are configured that contacting the tips 52 with a substrate (not shown) causes the template 36 to be spaced from the substrate by a desired distance. The cantilevers 50 and the tips 52 may be made of silicon, but should include an electrically-insulating material (e.g., silicon dioxide) where they approach or contact a substrate 54 of FIG. 7.

FIG. 7 is a schematic front view of a chip 34 in place over an exemplary substrate 54 during a flash lithographic process according to an embodiment of the present invention. The substrate 54 includes a graphene layer 56 on a silicon dioxide insulating layer 58 formed on a silicon chip 60. The arms 50 and tips 52 of the position sensor 44 maintain a set distance between the template 36 and the graphene layer 56. A water meniscus 62 forms between the sharp edge 38 of the template 36 and the graphene layer 56. The position sensor 44 is supported by an AFM (not shown), which also applies an electrical potential across the position sensor 44 and the substrate 54 to drive the oxidation reaction. The meniscus 62 provides the only direct electrical contact between the template 36 and the substrate 54.

FIG. 8 is a schematic orthogonal top view of the substrate 54 after completion of the flash lithographic step. An S-shaped portion 64 of the graphene layer 56 has been removed by oxidation and volatilization of the resulting CO₂. Removal of the S-shaped portion 64 has exposed the silicon dioxide layer 58, which does not oxidize.

The exemplary flash lithography process disclosed herein can be applied to more complex patterns than that discussed with respect to FIGS. 5-8. FIG. 9 is schematic illustration of a templated silicon chip 66 that includes an electrically-conductive template 68 that is suitable for forming a single-electron transistor such as transistor 32 of FIG. 4. The template 68 is formed with sharp edges, such as sharp edges 70, which may have widths in the range of from about 10 nm to about 30 nm. In all other respects the chip 66 is similar to the chip 34 of FIG. 5.

FIG. 10 is a schematic front view of the chip 66 in place over an exemplary substrate 72 during a flash lithographic process according to an embodiment of the present invention. In practice, the chip 66 would be mounted in a position sensor, such as the position sensor 44 discussed with respect to FIGS. 6 and 7. The substrate 72 includes a graphene layer 74 on a silicon dioxide insulating layer 76 formed on a silicon chip 78. A water meniscus 79 forms between the sharp edges 70 of the template 68 and the graphene layer 74, and has the contours of the template 68. In all other respects, the flash lithography step may be same as that described with respect to FIG. 7.

FIG. 11 is a schematic orthogonal top view of the substrate 72 after completion of the flash lithographic step. Trenches 80 have been formed by removal of the graphene layer 74 by oxidation and volatilization of the resulting CO₂. Removal of the lines 80 has exposed the silicon dioxide layer 76. The resulting trenches 80 match those of the template 68 and the transistor 32 of FIG. 4.

FIGS. 12A-12G are a sequenced set of schematic diagrams illustrating an exemplary method of forming templates, such as template 36 of FIG. 5 and template 68 of FIG. 9, for use in a flash lithography process according to an embodiment of the present invention.

Referring to FIG. 12A, a layer 82 of silicon dioxide, a few nanometers thick, is formed on a surface 84 of a n-type ultra-flat silicon chip 86.

Referring to FIG. 12B, a pattern 88 in the shape of the desired template is formed by spin-coating a layer (not shown) of a high-resolution electron-beam resist (e.g., hydrogen silsesquioxane, ZEP-520, Zeon Corp., Tokyo, Japan) onto the silicon dioxide layer 82, defining the pattern 88 by electron-beam lithography, and removing the excess resist with a solvent (e.g., acetone) to expose the silicon dioxide 82 outside of the pattern 86. Electron-beam lithography may be used to define patterns having line widths as small as about 20 nm.

Referring to FIG. 12C, the exposed silicon dioxide is then etched away (e.g., by a HF/NH₄F solution or CH₄ reactive etching) to create a silicon dioxide mask 90 for the silicon chip 86.

Referring to FIGS. 12C and 12D, the electron-beam resist pattern 88 is removed, the portion of the silicon surface 84 outside of the silicon dioxide mask 90 is etched away (e.g., by Cl₂ and HBr plasma etching) to a desired thickness, and the silicon dioxide mask 90 is etched away, leaving behind a silicon layer 92 with a raised template 94.

Referring to FIG. 12E, the silicon layer 92 and template 94 are subjected to low-temperature oxidation (e.g., at a temperature of 950° C.) to sharpen the contours of the template 94, depositing silicon dioxide to a thickness of about 1-2 nm and forming a sharp edge 96, followed by ion implantation of boron to make the template 94 electrically-conductive. A heavy dose of boron may be needed to provide an adequate electrical conductivity in the template. The boron may be activated by annealing at a temperature of about 950° C. in nitrogen gas for about 30 minutes.

Referring to FIG. 12F, a photoresist layer 98 is spin-coated over the template 94 and adjacent portions of the silicon layer 92, and a metallic layer 100 (e.g., a layer of nickel) is deposited on the back-side 102 of the silicon chip 86 so that it may provide an electrical and magnetic connection to an AFM. In an embodiment of the present invention, the metallic layer 100 is formed to a thickness in the range of from about 100 nm to about 200 nm.

Referring to FIG. 12G, the photoresist layer 98 is removed, exposing at least the template 94 formed on the silicon chip 86.

FIG. 13 is a schematic illustration of the chip 86 mounted to a silicon block 104, such that the template 94 faces away from the block 104. The block 104 is provided with spacers 106, 108, 110, 112 positioned around the chip 86. The spacers 106, 108, 110, 112 are made of an electrically-insulating material and may be formed by deposition of silicon dioxide onto the silicon block 104 by methods known in the art. The spacers 106, 108, 110, 112 extend past the template 94 such that contacting the spacers 106, 108, 110, 112 with a substrate (not shown) causes the template 94 to be spaced away from the substrate by a desired distance.

FIG. 14 is a schematic front view of the chip 86 in place over an exemplary substrate 114 during a flash lithographic process according to an embodiment of the present invention. The substrate 114 includes a graphene layer 116 on a silicon dioxide insulating layer 118 formed on a silicon chip 120. The spacers 106, 108, 110, 112 maintain a set distance between the template 94 and the graphene layer 116. A water meniscus 122 forms between the sharp edge 96 of the template 94 and the graphene layer 116. The block 104 is supported by an AFM (not shown), which also applies an electrical potential across the block 104 and substrate 114 to drive the oxidation reaction.

FIGS. 15A-15I are a sequenced set of schematic diagrams illustrating a method for fabricating a position sensor 124 (see FIGS. 15H and 15I) of the same type as the position sensor 44 discussed with respect to FIGS. 6 and 7. In all of the illustrated steps of the method (i.e., FIGS. 15A-15I), the views are end views taken from the same direction as the end view of the position sensor 124 shown in FIG. 15I.

Referring to FIG. 15A, layers 126, 128 of a positive electron beam resist are applied to the backside 130 of a silicon-on-insulator (SOI) wafer 132 in contact with the layers 126, 128 to protect the backside 130 of the SOI 132 during subsequent processing steps. The layers 126, 128 are formed by well-known methods of spin-coating and electron-beam lithography.

Referring to FIG. 15B, a metallic layer 134 (e.g., a layer of nickel) is deposited on the exposed area 136 of the backside 130 of the SOI wafer 132 so that the position sensor 124 may be electrically and magnetically connected to an AFM (note shown). In an embodiment of the present invention, the metallic layer 134 has a thickness in the range of from about 100 nm to about 200 nm.

Referring to FIG. 15C, a negative photoresist 138 is patterned onto the front side 140 of the SOI wafer 132 so as to define an exposed area 142 of the front side 140. Silicon is then etched from the exposed area 142. The silicon etching may be performed by methods using Cl₂ and HBr, or other methods known in the art.

Referring to FIG. 15D, the aforementioned silicon etching creates a recess 144 for receiving a templated chip 146 (see FIG. 16) of the same type discussed with respect to FIGS. 5, 9 and 12A-12G. The negative photoresist 138 is then removed (e.g., by use of acetone) from areas 148, 150.

Referring to FIG. 15E, removal of the negative photoresist 138 exposes portions (not shown) of the front side 140 of the SOI wafer 132 corresponding to areas 148, 150. Layers 152, 154 of silicon dioxide, layers 156, 158 of silicon, and layers 160, 162 of silicon dioxide are exposed at the front side 140 using techniques described in J. Han et al., J. Micromech. Microeng. (2006), vol. 16, pp. 198-204 (hereinafter, “the Han Article”), which is incorporated by reference herein in its entirety. Additional layers 164, 166 of silicon dioxide are added to the backside 130 of the SOI wafer 132, to protect the SOI wafer 132 in contact with the silicon dioxide layers 164, 166.

Referring to FIG. 15F, a layer of photoresist 168 is formed over the backside 130 of the SOI wafer 132 and the silicon dioxide layers 164, 166 to protect them during subsequent etching steps, and the upper silicon dioxide layers 152, 154 are etched so as to leave silicon dioxide remnants 170, 172 to protect the ends 174, 176 of the silicon layers 156, 158, where conical tips 174, 176 (see FIGS. 15G-15H) will be formed distal to the SOI wafer 132. Silicon layers 164, 166 are etched, and silicon dioxide remnants 170, 172 are removed to form conical tips 174, 176, according to methods described in the Han Article.

Referring to FIG. 15G, the conical tips 174, 176 extend transversely from the etched silicon layers 156, 158. The etched silicon layers 156, 158, in combination with the respective conical tips 174, 176 are referred to hereinafter as cantilevers 178, 180. The photoresist 168 is removed and the back side 130 of the SOI wafer 132 is etched, followed by etching of silicon dioxide layers 160, 162, 164, 166 (e.g., by using tetramethylammonium hydroxide at 80° C.) to free the cantilevers 178, 180. The cantilevers 178, 180, especially including the tips 174,176, are made non-conductive by the deposition of silicon dioxide layers 182, 184, 186, 188. Silicon dioxide layers 186, 188 should generally conform to the underlying tips 174, 176. The photoresist 138 is then removed. The completed position sensor 124 is shown in end view in FIG. 15I.

FIG. 16 shows a templated chip 136 situated in the recess 144 of the position sensor 124. The templated chip 136 may be of the same type as templated chips 34, 66, 86 discussed with respect to FIGS. 5, 9 and 12A-12G, respectively. FIG. 17 is a bottom orthogonal view of the position sensor 124 with the templated chip 136 showing another view of the cantilevers 178, 180, and additional cantilevers 182, 184 formed by an extension of the method discussed with respect to FIGS. 15E-15I. The necessary steps of such an extension will be recognized by those having ordinary skill in the art and possession of the present disclosure. The position sensor 124 can be magnetically mounted to a conventional AFM scanner head.

The position sensor 124 can be used as part of a sensor in a system for controlling the position and orientation of a templated chip relative to a substrate. The components of the system and their arrangement are not illustrated by a figure, but are described in sufficient detail herein to enable a person having ordinary skill in the art to comprehend and construct such a system. Components of position sensor 124 are numbered with reference to FIGS. 16 and 17.

Position sensing may be accomplished using a light lever technique. In an embodiment of the present invention, the position sensor 124 is mounted on the scanner head of an AFM, which moves the position sensor 124. Separate laser beams are directed at each of the cantilevers 178, 180, 182, 184 from the backside 130 of the position sensor 124. In an embodiment of the present invention, a beam from a single laser source is split by beam splitters to generate separate laser beam for each cantilever 178, 180, 182, 184. Each laser beam is reflected off of the cantilever and onto the center of a four-quadrant diode, which is a device well-known in the art. As a cantilever 178, 180, 182, 184 is brought closer to the substrate, electrostatic forces cause it to deflect in the z-direction and laterally. This deflection is seen as a change in the position of the reflected laser beam and measured as a voltage differential between the top-bottom and left-right halves of the photodiode. Voltage differentials for the respective diodes can be compared through a simple feedback loop. This system will continuously monitor the position and orientation of the position sensor 124 relative to the substrate, allowing for manual or automatic control.

The disclosed nanolithography technique can reproducibly transfer a pattern to a large area of substrate by a single application of voltage. Arrays of such patterns can be fabricated in a short amount of time simply by changing the lateral position of the templated chip. High reproducibility is achieved since the short patterning time and the rigidity of the templated chip configuration fortifies the technique against thermal or mechanical instability. Table 1 presents a comparison of an embodiment of the present invention with lithography techniques in the prior art.

TABLE 1 Environ- Technique Throughput Resolution Pattern ment Cost AOL* Highly ~37 nm Arbitrary Ambient Very Parallel High EBL* Serial ~10 nm Arbitrary Vacuum High AEBL* Highly ~45 nm Arbitrary High Very Parallel Vacuum High NIL* Highly ~22 nm Arbitrary Ambient High Parallel IL* Highly ~40 nm Periodic Ambient Low Parallel AFM* Serial ~15 nm Arbitrary Ambient Fair Parallel Parallel ~15 nm Periodic Ambient Fair AFM* Arbitrary** Local Highly ~10-30 nm Arbitrary Ambient Low Oxidation Nanolitho- Parallel graphy *AOL: Advanced Optical Lithography; EBL; Electron Beam Lithography; AEBL: Advanced Electron Beam Lithography; NIL: Nanoimprint Lithography; IL: Interference Lithography; AFM: Single-Tip AFM oxidation Lithography. Parallel AFM: Multi-Tip AFM Lithography **An array of several tens to hundreds of AFM tips is capable of producing arbitrary patterns per tip, however this pattern is repeated per tip, thereby creating arrays of such patterns.

EXPERIMENTAL EXAMPLES

A series of experiments were conducted using single-tip anodic oxidation (i.e., point oxidation using a standard AFM tip) of graphene to define parameter ranges for the design of the nanolithographic processes of the present disclosure. Experiments were performed using a Pacific Nanotechnology Nano-I2 AFM.

Example 1

Single-tip local anodic oxidation was used to cut few-layer graphene (FLG) and inscribe insulating patterns on highly-ordered pyrolyzed graphite (HOPG) using a standard AFM tip. A bias of −10V was applied to the tip with no feedback in a high humidity atmosphere to create 0.5 nm trenches spaced 27 nm apart on FLG, and having depths of 0.5 nm. Under the same conditions, with the AFM in scan mode, non-volatile, electrically-insulating square patterns of graphene oxide were formed on HOPG. The squares had dimensions of about 50 μm×50 μm and line widths of about 600 nm to 800 nm.

Example 2

Local oxidation was used to segment multi-walled carbon nanotubes at selected points. A standard AFM tip was positioned over a selected point on a nanotube having a diameter of about 50 nm, and a bias of about −5 V was applied for 100 ms.

Example 3

Local oxidation of a graphene substrate using a standard AFM conductive diamond tip was performed to evaluate the effect of the distance between the tip and the substrate at high relative humidity (i.e., relative humidity greater than 60%) across a voltage range of −4V to −8V and a hold time of about 100 ms. Feature sizes obtained under the process conditions that were evaluated are presented in Table 2 and plotted in FIG. 18.

TABLE 2 Smallest Feature Voltage Setpoint (nm) Humidity Size (nm) −8 120 78% 287 −8 93 79% 299 −8 82 78% 301 −8 75 72% 312 −8 61 76% 334 −8 56 78% 365 −8 43 78% 366 −8 37 76% 390 −8 24 72% 414 −8 18 72% 450 −6 120 76% 158 −6 82 62% 174 −6 59 62% 165 −6 50 77% 277 −6 45 78% 280 −6 24 78% 292 −5 120 77% 180 −5 99 66% 183 −5 85 66% 197 −5 78 65% 189 −5 67 76% 233 −5 53 76% 247 −5 49 72% 251 −5 41 72% 258 −5 22 72% 287 −4 120 68% 101 −4 86 68% 131 −4 39 68% 149 −4 20 68% 178

Example 4

Local oxidation of a graphene substrate using a standard AFM conductive diamond tip was performed to evaluate the effect of the distance between the tip and the substrate at low relative humidity (i.e., relative humidity less than 30%) across a voltage range of −6V to −9V and a hold time of about 100 ms. Feature sizes obtained under the process conditions that were evaluated are presented in Table 3 and plotted in FIG. 19.

TABLE 3 Smallest Feature Voltage Setpoint (nm) Humidity Size (nm) −9 100 29% 109 −9 94 29% 114 −9 83 29% 132 −9 76 29% 127 −9 62 29% 144 −9 56 29% 165 −9 43 29% 166 −9 39 29% 190 −9 23 29% 207 −9 17 29% 234 −8 50 28% 110 −8 48 28% 116 −8 44 28% 121 −8 35 28% 133 −8 30 28% 146 −8 29 27% 171 −8 18 27% 197 −8 10 27% 200 −6 50 26% 61 −6 45 26% 88 −6 43 26% 101 −6 34 26% 95 −6 29 26% 119 −6 18 26% 143 −6 0 26% 155

Example 5

Local oxidation of a graphene substrate using a standard AFM conductive diamond tip was performed to evaluate the effect of the voltage holdtime on feature size. Tests were made at an applied voltage of −7.85 V, a relative humidity of about 33%, and a tip/substrate distance of 45-50 nm. Feature sizes obtained under the process conditions that were evaluated are presented in Table 4 and plotted in FIG. 20.

TABLE 4 Hold Time (ms) Feature Size (nm) 70 128.8 60 112.5 50 99 40 75.3 30 69 20 58

It should be understood that the embodiments described herein are merely exemplary and that a person skilled in the art may make many variations and modifications thereto without departing from the spirit and scope of the present invention. All such variations and modifications, including those discussed above, are intended to be included within the scope of the invention, which is described, in part, in the claims presented below. 

1. A method of reproducibly forming a pattern having a nanoscale dimension in an oxidizable substrate, wherein said method employs a wafer having an electrically-conductive raised template integral therewith, the template having an electrically-conductive edge that is distal from the wafer, has a width that is less than about 30 nm and describes a pattern having a length of at least 1000 nm along one dimension of the pattern, said method comprising the steps of: in a gaseous media having a relative humidity of at least 20%, positioning the template with the sharp edge proximate the oxidizable substrate so as to form a meniscus of liquid water that fluidly and electrically connects the sharp edge to the substrate; and applying a voltage across the template and the substrate so as to oxidize at least some of a portion of the substrate that is in contact with the meniscus. 